This invention relates to a token passing network and a method for scheduling Built-In Self-Test (BIST) in a plurality of stages in memory elements based on: a matrix and ring structure of resource controllers, e.g., Scheduled BIST Resource Interface controllers (SBRICs), controlling the memory elements; executing BIST in stages to optimize efficiency of such testing; and passing a token to initiate processing between sets of SBRICs in the matrix via a level signal rather than a pulse signal to ensure that the token is received.
The scale of integration of memory elements, for example Regular Structure semiconductor elements (such as RAMs, ROMs, CAMs, FIFOs or Embedded Cores) and Random Logic elements, has increased in modern digital circuits in order to increase the circuit's functionality. The increased density has also heightened the difficulty of testing such circuits with conventional external testing machines. Consequently, much effort has been devoted to "Design for Testability" approaches, including designing memory elements with BIST capability, that is, the capability to test themselves.
However, BIST capability within memory elements of Very Large Scale Integrated (VLSI) circuits has not eliminated the difficulty of testing. The testing of a VLSI circuit including a variety of BISTed elements (i.e., elements having BIST capability) requires that an interface be provided within the circuit to couple control signals between a test controller and the BISTed memory elements to initiate and schedule BIST efficiently.
One approach is described in U.S. Pat. No. 5,570,374 to Yau et al., which is assigned to Lucent Technologies, Inc. This patent is incorporated in its entirety herein by reference. This patent provides a BIST network, including at least two BISTed elements (for example, each comprising a RAM, ROM, FIFO or a Random Logic element). The control network comprises at least one SBRIC which controls one or more Regular Structure BISTed memory elements (such SBRIC is hereinafter referred to as the SBRIC.sub.-- RS, and the memory elements with Regular Structure BIST are hereinafter referred to as RSB elements). In addition, the network comprises a plurality of SBRIC.sub.-- RSs serially coupled in a daisy chain. The first SBRIC.sub.-- RS in the chain serves to initiate self-testing of a first group of RSB elements which are coupled to the SBRIC.sub.-- RS in parallel. Each successive SBRIC RS in the chain is responsive to a control signal generated by a previous SBRIC.sub.-- RS in the chain and serves to initiate self-testing of the RSB elements in the corresponding successive group associated with that SBRIC.sub.-- RS so that groups of RSB elements are tested in sequence. In addition, since each of the SBRIC.sub.-- RSs runs on the same clock, they run on different clocks than the RSB elements they control.
There are several disadvantages of the approach described in the above patent. The serial coupling of the SBRIC.sub.-- RSs limits processing to a single SBRIC.sub.-- RS at a time. We have found that due to limitations on the number and type of RSB elements a single SBRIC.sub.-- RS can control, this feature reduces the network's efficiency in testing a large number of different RSB elements at one time.
Another disadvantage is that the network is limited to one pass for each SBRIC.sub.-- RS. That is, at the end of processing for the last SBRIC.sub.-- RS in the serial daisy chain, no further processing by any SBRIC.sub.-- RS can occur. Accordingly, where BIST testing includes a waiting period (for example, for retention testing), there is no means for initiating the processing of another one of the SBRIC.sub.-- RS elements during the waiting period. In addition, where the BIST of more than one SBRIC.sub.-- RS includes a waiting period, each SBRIC.sub.-- RS must implement a waiting period separately rather than applying a single such waiting period to several SBRIC.sub.-- RSs.
Since each of the SBRIC.sub.-- RSs runs on the same clock, they do not run on the same clock as their RSB elements. This results in asynchronous processing between each SBRIC.sub.-- RS and its RSB elements. As a result, we have found that the signals transmitted between a SBRIC.sub.-- RS and its group of RSB elements may be lost.
An additional disadvantage is that the network's behavior cannot be modified once it is implemented. For example, one or more SBRIC.sub.-- RSs cannot be disabled from processing their RSB elements in order to improve efficiency of the network. Such functionality can apply where a SBRIC.sub.-- RS in position after others in the chain enters its fail state to indicate that at least one of its RSB elements failed BIST testing and the faulty RSB element is replaced. However, each of the SBRIC.sub.-- RSs must rerun BIST rather than limiting BIST processing to solely the SBRIC.sub.-- RS element having the replaced RSB element.
Therefore, there is a need to improve a BIST control network for scheduling the self-testing of a plurality of different types of BISTed memory elements.